Proceedings Paper
Methodology for analyzing and quantifying design style changes and complexity using topological patterns| Format | Member Price | Non-Member Price |
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Paper Abstract
In order to maximize yield, IC design companies spend a lot of effort to analyze what types of design styles are needed and used in their layouts (standard cells, macros, routing layers, and so forth). This paper introduces a novel methodology for full chip high performance topological pattern analysis and the applications of this methodology towards analyzing design styles in order to quantify and measure design changes and the degree of layout regularization. This new approach allows engineers to perform a full profiling across all patterns that exist in design and without needing to explicitly specify what patterns to analyze.
Paper Details
Date Published: 16 March 2016
PDF: 13 pages
Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 978108 (16 March 2016); doi: 10.1117/12.2220021
Published in SPIE Proceedings Vol. 9781:
Design-Process-Technology Co-optimization for Manufacturability X
Luigi Capodieci, Editor(s)
PDF: 13 pages
Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 978108 (16 March 2016); doi: 10.1117/12.2220021
Show Author Affiliations
Jason P. Cain, Advanced Micro Devices, Inc. (United States)
Ya-Chieh Lai, Cadence Design Systems, Inc. (United States)
Ya-Chieh Lai, Cadence Design Systems, Inc. (United States)
Frank Gennari, Cadence Design Systems, Inc. (United States)
Jason Sweis, Cadence Design Systems, Inc. (United States)
Jason Sweis, Cadence Design Systems, Inc. (United States)
Published in SPIE Proceedings Vol. 9781:
Design-Process-Technology Co-optimization for Manufacturability X
Luigi Capodieci, Editor(s)
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