
Proceedings Paper
Investigation of coat-develop track system for placement error of contact hole shrink processFormat | Member Price | Non-Member Price |
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Paper Abstract
Directed Self-Assembly (DSA) is a well-known candidate for next generation sub-15nm half-pitch lithography. [1-2] DSA processes on 300mm wafers have been demonstrated for several years, and have given a strong impression due to finer pattern results. [3-4] On t he other hand, specific issues with DSA processes have begun to be clear as a result of these recent challenges. [5-6] Pattern placement error, which means the pattern shift after DSA fabrication, is recognized as one of these typical issues. Coat-Develop Track systems contribute to the DSA pattern fabrication and also influence the DSA pattern performance.[4] In this study, the placement error was investigated using a simple contact-hole pattern and subsequent contact-hole shrink process implemented on the SOKUDO DUO track. Thus, we will show the placement error of contact-hole shrink using a DSA process and discuss the difference between DSA and other shrink methods.
Paper Details
Date Published: 1 April 2016
PDF: 7 pages
Proc. SPIE 9777, Alternative Lithographic Technologies VIII, 97770O (1 April 2016); doi: 10.1117/12.2219925
Published in SPIE Proceedings Vol. 9777:
Alternative Lithographic Technologies VIII
Christopher Bencher, Editor(s)
PDF: 7 pages
Proc. SPIE 9777, Alternative Lithographic Technologies VIII, 97770O (1 April 2016); doi: 10.1117/12.2219925
Show Author Affiliations
Masahiko Harumoto, SCREEN Semiconductor Solutions Co., Ltd. (Japan)
Harold Stokes, SCREEN SPE Germany GmbH (Germany)
Yuji Tanaka, SCREEN Semiconductor Solutions Co., Ltd. (Japan)
Koji Kaneyama, SCREEN Semiconductor Solutions Co., Ltd. (Japan)
Charles Pieczulewski, SCREEN Semiconductor Solutions Co., Ltd. (Japan)
Masaya Asai, SCREEN Semiconductor Solutions Co., Ltd. (Japan)
Harold Stokes, SCREEN SPE Germany GmbH (Germany)
Yuji Tanaka, SCREEN Semiconductor Solutions Co., Ltd. (Japan)
Koji Kaneyama, SCREEN Semiconductor Solutions Co., Ltd. (Japan)
Charles Pieczulewski, SCREEN Semiconductor Solutions Co., Ltd. (Japan)
Masaya Asai, SCREEN Semiconductor Solutions Co., Ltd. (Japan)
Isabelle Servin, CEA-LETI MINATEC (France)
Maxime Argoud, CEA-LETI MINATEC (France)
Ahmed Gharbi, CEA-LETI MINATEC (France)
Celine Lapeyre, CEA-LETI MINATEC (France)
Raluca Tiron, CEA-LETI MINATEC (France)
Cedric Monget, STMicroelectronics (France)
Maxime Argoud, CEA-LETI MINATEC (France)
Ahmed Gharbi, CEA-LETI MINATEC (France)
Celine Lapeyre, CEA-LETI MINATEC (France)
Raluca Tiron, CEA-LETI MINATEC (France)
Cedric Monget, STMicroelectronics (France)
Published in SPIE Proceedings Vol. 9777:
Alternative Lithographic Technologies VIII
Christopher Bencher, Editor(s)
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