Share Email Print

Proceedings Paper

Characterization of shallow trench isolation CMP process and its application
Author(s): Helen Li; ChunLei Zhang; JinBing Liu; ZhengFang Liu; Kuang Han Chen; Tamba Gbondo-Tugbawa; Hua Ding; Flora Li; Brian Lee; Aaron Gower-Hall; Yang-Chih Chiu
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

Chemical mechanical polishing (CMP) has been a critical enabling technology in shallow trench isolation (STI), which is used in current integrated circuit fabrication process to accomplish device isolation. Excessive dishing and erosion in STI CMP processes, however, create device yield concerns. This paper proposes characterization and modeling techniques to address a variety of concerns in STI CMP. In the past, majority of CMP publications have been addressed on interconnect layers in backend- of-line (BEOL) process. However, the number of CMP steps in front-end-of-line (FEOL) has been increasing in more advanced process techniques like 3D-FinFET and replacement metal gate, as a results incoming topography induced by FEOL CMP steps can no longer be ignored as the topography accumulates and stacks up across multiple CMP steps and eventually propagating to BEOL layers. In this paper, we first discuss how to characterize and model STI CMP process. Once STI CMP model is developed, it can be used for screening design and detect possible manufacturing weak spots. We also work with process engineering team to establish hotspot criteria in terms of oxide dishing and nitride loss.

As process technologies move from planar transistor to 3D transistor like FinFet and multi-gate, it is important to accurately predict topography in FEOL CMP processes. These incoming topographies when stacked up can have huge impact in BEOL copper processes, where copper pooling becomes catastrophic yield loss. A calibration methodology to characterize STI CMP step is developed as shown in Figure 1; moreover, this STI CMP model is validated from silicon data collected from product chips not used in calibration stage. Additionally, wafer experimental setup and metrology plan are instrumental to an accurate model with high predictive power.

After a model is generated, spec limits and threshold to establish hotspots criteria can be defined. Such definition requires working closely with foundry process engineering and integration team and reviewing past failure analysis (FA) to come up a reasonable metrics. Conventionally, a potential STI weak point can be found when nitride residues remains in the active region after nitride strip. Another source of STI hotspots occurs when nitride erosion is too much, and active region can suffer severe damage.

Paper Details

Date Published: 16 March 2016
PDF: 6 pages
Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 978113 (16 March 2016); doi: 10.1117/12.2219912
Show Author Affiliations
Helen Li, Semiconductor Manufacturing International Corp. (China)
ChunLei Zhang, Semiconductor Manufacturing International Corp. (China)
JinBing Liu, Semiconductor Manufacturing International Corp. (China)
ZhengFang Liu, Semiconductor Manufacturing International Corp. (China)
Kuang Han Chen, Cadence Design Systems, Inc. (United States)
Tamba Gbondo-Tugbawa, Cadence Design Systems, Inc. (United States)
Hua Ding, Cadence Design Systems, Inc. (United States)
Flora Li, Cadence Design Systems, Inc. (United States)
Brian Lee, Cadence Design Systems, Inc. (United States)
Aaron Gower-Hall, Cadence Design Systems, Inc. (United States)
Yang-Chih Chiu, Cadence Design Systems, Inc. (United States)

Published in SPIE Proceedings Vol. 9781:
Design-Process-Technology Co-optimization for Manufacturability X
Luigi Capodieci, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?