As process window margins for cutting edge DUV lithography continue to shrink, the impact of systematic patterning defects on final yield increases. Finding process window limiting hot spot patterns and monitoring them in high volume manufacturing (HVM) is increasingly challenging with conventional methods, as the size of critical defects can be below the resolution of traditional HVM inspection tools. We utilize a previously presented computational method of finding hot spot patterns by full chip simulation and use this to guide high resolution review tools by predicting the state of the hot spots on all fields of production wafers. In experiments with a 10nm node Metal LELELE vehicle we show a 60% capture rate of after-etch defects down to 3nm in size, at specific hot spot locations. By using the lithographic focus and dose correction knobs we can reduce the number of patterning defects for this test case by ~60%.

Date Published: 8 March 2016
PDF: 10 pages
Proc. SPIE 9778, Metrology, Inspection, and Process Control for Microlithography XXX, 97781R (8 March 2016); doi: 10.1117/12.2219906

Published in SPIE Proceedings Vol. 9778:
Metrology, Inspection, and Process Control for Microlithography XXX
Martha I. Sanchez, Editor(s)