Computer simulation of lithographic performance, including resist CD, film thickness, sidewall angle and profile has been extensively studied during the past three decades. Lithography simulation has been widely adopted as an enabling technology for high-volume chip manufacturing. However, measurement artifacts arising from CD-SEM metrology are typically ignored in simulation, due to the difficulty of accurately modeling the effect of the CD-SEM at acceptable computational speed. In this paper, we demonstrate how CD measurements can be improved by including a fast, compact CD-SEM model. For example, the variation in effective resist metrology height along contour lines extracted from a simulated CD-SEM image is characterized for a range of structures through focus. We also demonstrate how SEM settings affect the shape of extracted SEM contour and metrology height at contour edge. The Edge Placement Error (EPE) caused by SEM artifact is carefully studied.

Date Published: 24 March 2016
PDF: 13 pages
Proc. SPIE 9778, Metrology, Inspection, and Process Control for Microlithography XXX, 97780B (24 March 2016); doi: 10.1117/12.2219776

Published in SPIE Proceedings Vol. 9778:
Metrology, Inspection, and Process Control for Microlithography XXX
Martha I. Sanchez, Editor(s)