As technology moves towards more advanced nodes, the complexity of VLSI designs continues to grow and unexpected designs in physical layout push the process limits. In the beginning of a new technology node development there are not enough real design chips with complex structures and it is hard for foundries to comprehensively verify their process capabilities. It is necessary for foundries to generate a comprehensive set of test patterns to co-optimize the design rule manual (DRM) and manufacturing process. Furthermore, as the technology goes into an accelerated yield ramp phase, we need to find the potential process weak-points and identify the gaps between the design rules and the process.

This paper will present a novel methodology to enumerate initial test patterns based on other technology node products. With this novel methodology, DRM development and process capability verification can be sped up rapidly in comparison to a more traditional way. At the same time, the process weak-point signatures can be migrated from the older technology nodes to the new technology node for verification. This methodology will help foundries catch process detractor patterns at new technology early development stage.

Date Published: 16 March 2016
PDF: 7 pages
Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 97810L (16 March 2016); doi: 10.1117/12.2219561

Published in SPIE Proceedings Vol. 9781:
Design-Process-Technology Co-optimization for Manufacturability X
Luigi Capodieci, Editor(s)