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Improving scanner wafer alignment performance by target optimization
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Paper Abstract

In the process nodes of 10nm and below, the patterning complexity along with the processing and materials required has resulted in a need to optimize alignment targets in order to achieve the required precision, accuracy and throughput performance. Recent industry publications on the metrology target optimization process have shown a move from the expensive and time consuming empirical methodologies, towards a faster computational approach. ASML’s Design for Control (D4C) application, which is currently used to optimize YieldStar diffraction based overlay (DBO) metrology targets, has been extended to support the optimization of scanner wafer alignment targets. This allows the necessary process information and design methodology, used for DBO target designs, to be leveraged for the optimization of alignment targets. In this paper, we show how we applied this computational approach to wafer alignment target design. We verify the correlation between predictions and measurements for the key alignment performance metrics and finally show the potential alignment and overlay performance improvements that an optimized alignment target could achieve.

Paper Details

Date Published: 24 March 2016
PDF: 7 pages
Proc. SPIE 9778, Metrology, Inspection, and Process Control for Microlithography XXX, 97782M (24 March 2016); doi: 10.1117/12.2219491
Show Author Affiliations
Philippe Leray, IMEC (Belgium)
Christiane Jehoul, IMEC (Belgium)
Robert Socha, ASML Netherlands B.V. (Netherlands)
Boris Menchtchikov, ASML Netherlands B.V. (Netherlands)
Sudhar Raghunathan, ASML Netherlands B.V. (Netherlands)
Eric Kent, ASML Netherlands B.V. (Netherlands)
Hielke Schoonewelle, ASML Netherlands B.V. (Netherlands)
Patrick Tinnemans, ASML Netherlands B.V. (Netherlands)
Paul Tuffy, ASML Netherlands B.V. (Netherlands)
Jun Belen, LAM Research Corp. (United States)
Rich Wise, LAM Research Corp. (United States)

Published in SPIE Proceedings Vol. 9778:
Metrology, Inspection, and Process Control for Microlithography XXX
Martha I. Sanchez, Editor(s)

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