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Proceedings Paper

Eliminating the offset between overlay metrology and device patterns using computational metrology target design
Author(s): Jianming Zhou; Sarah Wu; Craig Hickman; Ewoud van West; Maurits van der Schaar; Wangshi Zhou; Youping Zhang; Sean Park; Paul Tuffy; Dan Ulmer; Cedric Affentauschegg; Henk Niesing
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Paper Abstract

Designing metrology targets that mimic process device cell behavior is becoming a common component in overlay process control. For an advanced DRAM process (sub 20 nm node), the extreme illumination methods needed to pattern the critical device features makes it harder to control the aberration induced overlay delta between metrology target and device patterns. To compensate for this delta, a Non-Zero-Offset is applied to the metrology measurement that is based on a manual calibration measurement using CD-SEM Overlay. In this paper, we document how this mismatch can be minimized through the right choice of metrology targets and measurement recipe.

Paper Details

Date Published: 20 October 2016
PDF: 11 pages
Proc. SPIE 9778, Metrology, Inspection, and Process Control for Microlithography XXX, 97781G (20 October 2016); doi: 10.1117/12.2219439
Show Author Affiliations
Jianming Zhou, Micron Technology, Inc. (United States)
Sarah Wu, Micron Technology, Inc. (United States)
Craig Hickman, Micron Technology, Inc. (United States)
Ewoud van West, ASML US, Inc. (United States)
Maurits van der Schaar, ASML Netherlands B.V. (Netherlands)
Wangshi Zhou, ASML US, Inc. (United States)
Youping Zhang, ASML US, Inc. (United States)
Sean Park, ASML US, Inc. (United States)
Paul Tuffy, ASML US, Inc. (United States)
Dan Ulmer, ASML Netherlands B.V. (Netherlands)
Cedric Affentauschegg, ASML Netherlands B.V. (Netherlands)
Henk Niesing, ASML Netherlands B.V. (Netherlands)

Published in SPIE Proceedings Vol. 9778:
Metrology, Inspection, and Process Control for Microlithography XXX
Martha I. Sanchez, Editor(s)

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