In this paper, we examine two types of 2-D layout design methodology (via connecting and direct stitching) for future IC scaling. The yield model for via landing process is first developed based on the probability-of-success (POS) function, which incorporates the overlay errors and via CD variations. A layout library is constructed using the 2-D patterns in 45-nm and 15-nm open cell libraries, and the basic stitching structures are identified. Six commonly seen stitching structures in our layout library are analyzed. The optimization methods for via landing and direct stitching are discussed. We compare the yield performance of via landing and direct stitching (with and without optimization). It is found that direct-stitching yield is better than the via-landing yield for all types of vias in the 2-D layouts we examined, regardless of whether the optimization procedure is performed.

Date Published: 16 March 2016
PDF: 11 pages
Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 97810T (16 March 2016); doi: 10.1117/12.2219336

Published in SPIE Proceedings Vol. 9781:
Design-Process-Technology Co-optimization for Manufacturability X
Luigi Capodieci, Editor(s)