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Proceedings Paper

Using pattern enumeration to accelerate process development and ramp yield
Author(s): Linda Zhuang; Jenny Pang; Jessy Xu; Mengfeng Tsai; Amy Wang; Yifan Zhang; Jason Sweis; Ya-Chieh Lai; Hua Ding
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Paper Abstract

During a new technology node process setup phase, foundries do not initially have enough product chip designs to conduct exhaustive process development. Different operational teams use manually designed simple test keys to set up their process flows and recipes. When the very first version of the design rule manual (DRM) is ready, foundries enter the process development phase where new experiment design data is manually created based on these design rules. However, these IP/test keys contain very uniform or simple design structures. This kind of design normally does not contain critical design structures or process unfriendly design patterns that pass design rule checks but are found to be less manufacturable. It is desired to have a method to generate exhaustive test patterns allowed by design rules at development stage to verify the gap of design rule and process.

This paper presents a novel method of how to generate test key patterns which contain known problematic patterns as well as any constructs which designers could possibly draw based on current design rules. The enumerated test key patterns will contain the most critical design structures which are allowed by any particular design rule. A layout profiling method is used to do design chip analysis in order to find potential weak points on new incoming products so fab can take preemptive action to avoid yield loss. It can be achieved by comparing different products and leveraging the knowledge learned from previous manufactured chips to find possible yield detractors.

Paper Details

Date Published: 16 March 2016
PDF: 9 pages
Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 97810A (16 March 2016); doi: 10.1117/12.2219129
Show Author Affiliations
Linda Zhuang, Semiconductor Manufacturing International Corp. (China)
Jenny Pang, Semiconductor Manufacturing International Corp. (China)
Jessy Xu, Semiconductor Manufacturing International Corp. (China)
Mengfeng Tsai, Semiconductor Manufacturing International Corp. (China)
Amy Wang, Semiconductor Manufacturing International Corp. (China)
Yifan Zhang, Cadence Design Systems, Inc. (United States)
Jason Sweis, Cadence Design Systems, Inc. (United States)
Ya-Chieh Lai, Cadence Design Systems, Inc. (United States)
Hua Ding, Cadence Design Systems, Inc. (United States)

Published in SPIE Proceedings Vol. 9781:
Design-Process-Technology Co-optimization for Manufacturability X
Luigi Capodieci, Editor(s)

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