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Proceedings Paper

Die cost analysis through defect reduction for wafer fab equipment
Author(s): Vinay Binjrajka; Chander Jethani; Steven A. Brown
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Paper Abstract

This study provides a means of estimating the factory cost savings from defect reduction and yield improvement programs for wafer fabrication equipment. The process flow and toolset for a 0.25 micron design-rule factory manufacturing high performance logic devices are analyzed using SEMATECH's cost models. Scenarios with different sets of defect densities are evaluated and results are compared for cost per die, number of die produced, and probe yield. The various parameters analyzed and compiled are probe yield, die cost, and die cost by tool group. The defect density values are generated using SEMATECH's yield model. A Pareto analysis is provided to under stand cost benefits and prioritize potential equipment improvement programs. This effort allows SEMATECH and equipment manufactures to identify the most cost-effective defect reduction programs, thus improving capital productivity.

Paper Details

Date Published: 22 September 1995
PDF: 9 pages
Proc. SPIE 2635, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis, (22 September 1995); doi: 10.1117/12.221459
Show Author Affiliations
Vinay Binjrajka, Motorola (United States)
Chander Jethani, IBM Corp. (United States)
Steven A. Brown, Motorola (United States)

Published in SPIE Proceedings Vol. 2635:
Microelectronic Manufacturing Yield, Reliability, and Failure Analysis
Gopal Rao; Massimo Piccoli, Editor(s)

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