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Proceedings Paper

Material processing and advanced well structures using high-energy implantation for EPI replacement
Author(s): Dirk Wristers; Chris Eiting; Wes Morris; Dim-Lee Kwong; Jim Fulford
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Paper Abstract

With the cost of each new technology generation increasing at an alarming rate, it has become imperative that technologies which provide for process simplification and material cost reduction be seriously investigated. Many of the next generation technologies for logic as well as memory applications have incorporated some vertical modulation of the well dopant concentration. This type of structure can provide process simplification and an improved isolation strategy, but with more aggressive engineering of the substrate dopant concentration and the current gain of the parasitic bipolar transistors that exist in the CMOS structure superior, latch-up immunity has been demonstrated on both simulated and actual devices. Devices with an aggressive 2 micron P+ to N+ spacing were built with this innovative well structure and have been shown to provide outstanding latch-up performance (4X improvement in measured trigger current) as compared to that of devices built with a standard diffused well process. In addition to providing an analysis of the latch-up performance of the advanced well structure, results of an investigation of the impact of high energy implantation on the gate oxide quality, junction quality and bulk material properties is discussed.

Paper Details

Date Published: 22 September 1995
PDF: 12 pages
Proc. SPIE 2635, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis, (22 September 1995); doi: 10.1117/12.221455
Show Author Affiliations
Dirk Wristers, Advanced Micro Devices, Inc. (United States)
Chris Eiting, Advanced Micro Devices, Inc. (United States)
Wes Morris, Silicon Engineering (United States)
Dim-Lee Kwong, Univ. of Texas/Austin (United States)
Jim Fulford, Advanced Micro Devices, Inc. (United States)

Published in SPIE Proceedings Vol. 2635:
Microelectronic Manufacturing Yield, Reliability, and Failure Analysis
Gopal Rao; Massimo Piccoli, Editor(s)

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