Share Email Print

Proceedings Paper

Solving production process challenges with wafer-level reliability techniques
Author(s): J. Shideler; Joseph Reedholm; C.B. Chuck Yarling
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

Many major semiconductor fabs are beginning to implement wafer-level reliability (WLR) as a means to improve both quality and yield of their product. Presently available WLR test structures provide a method for the reliability engineer to monitor the reliability of advanced state- of-the-art devices manufactured from CMOS, Bipolar, and BiCMOS technologies. However, these test structures also provide statistical parameters resulting from 'integrated', i.e., multiple processes. This paper examines how in-line testing of presently available WLR test structures can enable the process engineer to uniquely examine various process control parameters. Results in the form of tables and control charts show that implementation of WLR in the manufacturing area provide data useful to process, equipment, and reliability engineers.

Paper Details

Date Published: 22 September 1995
PDF: 10 pages
Proc. SPIE 2635, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis, (22 September 1995); doi: 10.1117/12.221447
Show Author Affiliations
J. Shideler, National Semiconductor Corp. (United States)
Joseph Reedholm, Reedholm Instruments Co. (United States)
C.B. Chuck Yarling, EEESPEC (United States)

Published in SPIE Proceedings Vol. 2635:
Microelectronic Manufacturing Yield, Reliability, and Failure Analysis
Gopal Rao; Massimo Piccoli, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?