Share Email Print
cover

Proceedings Paper

Programmable real-time FIR-filter logic device
Author(s): Eduardo I. Boemo; F. Barbero; J. Faura; J. Jauregui; J. M. Meneses
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

This paper resumes the development of an integrate tool for designing high-speed, real-time, FIR-filter circuits. The system is composed of programmable IC and an associate software for filter repsonse analysis, synthesis of coefficients, and circuit programming. The architecture is highly regular, easily expandable and its control is distributed. The chip can be programmed by a PC or by using an EPROM. The prototypes have been fabricated using the CMOS 1.5micrometers Standard Cell of ES2. Moreover, some heuristics about multipliers upgrated to CMOS 1micrometers - Cadence DFWII are resumed.

Paper Details

Date Published: 19 September 1995
PDF: 8 pages
Proc. SPIE 2607, Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing, (19 September 1995); doi: 10.1117/12.221343
Show Author Affiliations
Eduardo I. Boemo, Univ. Politecnica de Madrid (Spain)
F. Barbero, Univ. Politecnica de Madrid (Spain)
J. Faura, Univ. Politecnica de Madrid (Spain)
J. Jauregui, Univ. Politecnica de Madrid (Spain)
J. M. Meneses, Univ. Politecnica de Madrid (Spain)


Published in SPIE Proceedings Vol. 2607:
Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing
John Schewel, Editor(s)

© SPIE. Terms of Use
Back to Top