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Proceedings Paper

Designing a partially reconfigured system
Author(s): J. D. Hadley; Brad L. Hutchings
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Paper Abstract

Partial reconfiguration is the ability of certain FPGAs to reconfigure only selected protions of the device while other portions contiue to operate undisturbed. When used in conjunction with the runtime reconfiguration (RTR) implementation strategy, the performance of the system can be greatly enhanced. RRANN2 is a RTR artifical neural network that uses partial reconfiguration. Its operation is divided into a series of sequentially executed stages with each stage implemented as a separate circuit module. System operation consists of sequencing through these modules at runtime, one configuraiton at a time. By carefully organizing each circuit module in order to establish a large number of functional and physical commonalities, partial reconfiguration is used to leave common circuitry resident on the FPGAs during system reconfiguration. Transitioning between configurations can then be accomplished by updating only the differences between circuit modules. This significantly enhances overall performance by reducing the amount of time the RTR application spends configuring. RRANN2 exhibited a 53.5% reduction in reconfiguration time through the use of partial reconfiguration. This paper presents the methodology used to design the RRANN2 system.

Paper Details

Date Published: 19 September 1995
PDF: 11 pages
Proc. SPIE 2607, Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing, (19 September 1995);
Show Author Affiliations
J. D. Hadley, Brigham Young Univ. (United States)
Brad L. Hutchings, Brigham Young Univ. (United States)

Published in SPIE Proceedings Vol. 2607:
Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing
John Schewel, Editor(s)

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