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Proceedings Paper

Statistical threshold-voltage variation and its impact on supply-voltage scaling
Author(s): David Burnett; Shih-Wei Sun
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Paper Abstract

A fundamental limit to the scaling of CMOS supply voltages (VCC) exists due to the statistical variation of MOSFET threshold voltage (VT). At the microscopic (device-to-device) level, an inherent variability in VT exists due to the randomness of the number of dopants in the depletion region of the MOSFET. As the number of dopants in the depletion region decreases with scaling, the VT variations will increase and become more significant. In addition to this fundamental variation in VT, systematic VT variations exist due to manufacturing fluctuations with the gate length, gate oxide thickness, implant uniformity, and anneal temperatures. For SRAM circuits, the VT mismatch caused by channel dopant fluctuations degrades the cell stability and limits the minimum operating voltage of the SRAM. For logic circuits, the systematic VT variations across a waver significantly increase the variation of the measured propagation delay on a wafer as VCC is scaled down towards the MOSFET VT. These limitations on VCC scaling pose additional challenges in the design and manufacturing of devices and circuits for low-power systems.

Paper Details

Date Published: 15 September 1995
PDF: 8 pages
Proc. SPIE 2636, Microelectronic Device and Multilevel Interconnection Technology, (15 September 1995); doi: 10.1117/12.221151
Show Author Affiliations
David Burnett, Motorola (United States)
Shih-Wei Sun, Motorola (United States)

Published in SPIE Proceedings Vol. 2636:
Microelectronic Device and Multilevel Interconnection Technology
Ih-Chin Chen; Girish A. Dixit; Trung Tri Doan; Nobuo Sasaki, Editor(s)

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