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Proceedings Paper

Development and production integration of a planarized AlCu interconnect process for submicron CMOS
Author(s): Kevin C. Brown; Rodney Hill; Krishna Reddy; Kamesh Gadepally
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Paper Abstract

A planarized aluminum alloy interconnect has been developed as an alternative to tungsten plugs for a 0.65 (mu) CMOS technology. Contact resistance can increase with either an inadequate RF sputter clean or titanium that is too thin to reduce the native oxide. Diffusion barrier results show that a minimum amount of titanium nitride, whether deposited conventionally or with collimation, is necessary for low junction leakage and good sort yield. Stacked contacts and vias are supported while via resistance and defect density are improved. Electrical bridging due to silicon residues from AlSiCu can be minimized with metal overetching, but not to the extent of AlCu. Sidewall pitting was observed to be due to galvanic corrosion from copper precipitate formation. Overall yield has been improved along with decreased wafer cost compared to conventional tungsten plug technology.

Paper Details

Date Published: 15 September 1995
PDF: 10 pages
Proc. SPIE 2636, Microelectronic Device and Multilevel Interconnection Technology, (15 September 1995); doi: 10.1117/12.221137
Show Author Affiliations
Kevin C. Brown, National Semiconductor Corp. (United States)
Rodney Hill, National Semiconductor Corp. (United States)
Krishna Reddy, National Semiconductor Corp. (United States)
Kamesh Gadepally, National Semiconductor Corp. (United States)

Published in SPIE Proceedings Vol. 2636:
Microelectronic Device and Multilevel Interconnection Technology
Ih-Chin Chen; Girish A. Dixit; Trung Tri Doan; Nobuo Sasaki, Editor(s)

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