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Proceedings Paper

Enhanced memory architecture for massively parallel vision chip
Author(s): Zhe Chen; Jie Yang; Liyuan Liu; Nanjian Wu
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Paper Abstract

Local memory architecture plays an important role in high performance massively parallel vision chip. In this paper, we propose an enhanced memory architecture with compact circuit area designed in a full-custom flow. The memory consists of separate master-stage static latches and shared slave-stage dynamic latches. We use split transmission transistors on the input data path to enhance tolerance for charge sharing and to achieve random read/write capabilities. The memory is designed in a 0.18 μm CMOS process. The area overhead of the memory achieves 16.6 μm2/bit. Simulation results show that the maximum operating frequency reaches 410 MHz and the corresponding peak dynamic power consumption for a 64-bit memory unit is 190 μW under 1.8 V supply voltage.

Paper Details

Date Published: 13 April 2015
PDF: 6 pages
Proc. SPIE 9522, Selected Papers from Conferences of the Photoelectronic Technology Committee of the Chinese Society of Astronautics 2014, Part II, 95220U (13 April 2015); doi: 10.1117/12.2179447
Show Author Affiliations
Zhe Chen, Institute of Semiconductors (China)
Jie Yang, Institute of Semiconductors (China)
Liyuan Liu, Institute of Semiconductors (China)
Nanjian Wu, Institute of Semiconductors (China)


Published in SPIE Proceedings Vol. 9522:
Selected Papers from Conferences of the Photoelectronic Technology Committee of the Chinese Society of Astronautics 2014, Part II
Xiangwan Du; Jennifer Liu; Dianyuan Fan; Jialing Le; Yueguang Lv; Jianquan Yao; Weimin Bao; Lijun Wang, Editor(s)

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