In this study, a hardware efficient field-programmable-gate-array (FPGA) implementation of the JPEG-LS encoder for lossless image compression is introduced. Encoder architecture comprises both regular mode and run mode with run interruption sample encoding procedures for full compliance with the ISO/ITU standard. Differently from former reported implementations, prediction error computation is optimized with pipeline data forwarding technique for optimum delay and minimum complexity. Besides, procedures of the run-length encoding are realized with normalization scheme using look-up tables without update latency. Synthesis results showed that proposed optimizations improved the processing speed of the encoder noticeably while FPGA hardware footprint is significantly reduced.

Date Published: 21 May 2015
PDF: 8 pages
Proc. SPIE 9501, Satellite Data Compression, Communications, and Processing XI, 950106 (21 May 2015); doi: 10.1117/12.2177882

Published in SPIE Proceedings Vol. 9501:
Satellite Data Compression, Communications, and Processing XI
Bormin Huang; Chein-I Chang; Chulhee Lee; Yunsong Li; Qian Du, Editor(s)