We provide an alternative architecture for the next generation datacenters by employing electronic and photonic switching cores. The capacity of electronic packet switching (EPS) cores is not enough for the bandwidth requirements of next generation datacenters. On the other hand, it is prohibitively costly to build pure photonic packet switching (OPS) core which is capable of switching native Ethernet frames in nanoseconds. We propose a low-cost hybrid OPS/EPS platform which significantly increases the switching capacity of datacenters for all traffic patterns while using the existing EPS cores. Our proposed architecture is a fat-tree hierarchy consisting of servers, top-of-racks (TOR), aggregation switches, and core switches. The aggregation switches are interconnected to the core hybrid OPS/EPS switch. Since the traffic inside datacenters is typically bimodal, the hybrid switch core becomes feasible by switching short and long packets using EPS and OPS cores, respectively. In order to prepare long packets for photonic switching, they undergo packet contention resolution, compression, and bitwise scrambling. Afterwards, a photonic destination label is added to the long packets, and they are sent out through an optical transmitter. For compressing the long packets, the clock rate is raised on the output of the physical layer. Packet compression increases inter-packet gap to insert the photonic label. Also, it provides more time for photonic switch connection set-up and receiver synchronization at the destination aggregation switch. We developed a test bed for our architecture and used it to transmit real-time traffic. Our experiments show successful transmission of all packets through OPS.

Date Published: 27 February 2015
PDF: 6 pages
Proc. SPIE 9367, Silicon Photonics X, 93670L (27 February 2015); doi: 10.1117/12.2177686

Published in SPIE Proceedings Vol. 9367:
Silicon Photonics X
Graham T. Reed; Michael R. Watts, Editor(s)