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Proceedings Paper

VLSI architecture of a programmable real-time video signal processor
Author(s): Peter Pirsch; Thomas Wehberg
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Paper Abstract

Coding schemes for data rate reduction of digital video signals are being devised for various application areas. Such applications call for video signal processors suited for real-time operation and realization with small size. Small size can be achieved using advanced VLSI technology. Real-time processing of video signals re- quires several 100 Mega operations per second (MOPS) and correspondingly high data rates for operand transport. These requirements can be met by multiprocessors employing parallelization and pipelining in an adapted architecture. In order to support distinct applications, the multiprocessors have to be programmable. The requirements of video coding schemes have been extracted and mapped into a multiprocessor architecture for programmable real-time video processing. In this contribution, the extracted requirements, the adapted architecture of a multiprocessor, and the multiprocessor modules are presented. The realization of several modules of the multiprocessor using CMOS technology is also reported.

Paper Details

Date Published: 1 November 1990
PDF: 11 pages
Proc. SPIE 1301, Digital Image Processing and Visual Communications Technologies in the Earth and Atmospheric Sciences, (1 November 1990); doi: 10.1117/12.21429
Show Author Affiliations
Peter Pirsch, Univ. Hannover (Germany)
Thomas Wehberg, Univ. Hannover (Germany)

Published in SPIE Proceedings Vol. 1301:
Digital Image Processing and Visual Communications Technologies in the Earth and Atmospheric Sciences
Paul Janota, Editor(s)

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