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Proceedings Paper

Yield enhancement through identifying design sensitivities
Author(s): Bei Tseng Bill Chu; Mark D. Kellam
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Paper Abstract

It is commonly recognized that there are three main causes of circuit yield losses: process related problems, design sensitivities, and point defects. Yield losses due to design sensitivity primarily occur during the early development phase of a VLSI circuit. Previous work in eliminating design sensitivities have concentrated on using statistical simulations which is computationally expensive for VLSI circuits with over million transistors. This paper describes an approach to detect design sensitivity using methods of pattern recognition and parsimonious hypothesis formation.

Paper Details

Date Published: 1 January 1990
PDF: 8 pages
Proc. SPIE 1293, Applications of Artificial Intelligence VIII, (1 January 1990); doi: 10.1117/12.21150
Show Author Affiliations
Bei Tseng Bill Chu, Univ. of North Carolina/Charlotte (United States)
Mark D. Kellam, Microelectronics Ctr. of North Carolina (United States)

Published in SPIE Proceedings Vol. 1293:
Applications of Artificial Intelligence VIII
Mohan M. Trivedi, Editor(s)

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