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Proceedings Paper

KIM200: a tagged-RISC architecture for gallium arsenide implementation
Author(s): Jean-Claude Heudin; Christophe Metivier
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Paper Abstract

This paper describes a new RISC architecture being designed to take advantage of GaAs technology for high performance symbolic processing. First, we present our top-down methodology which starts from the study of applications requirements, technology constraints, and concludes with the choice of the most suitable architecture. Then, next paragraphs describe carefully the architecture and its originalities. It can be summerized as a tagged-RISC embedded processor, which is able to operate with a 200 Mhz clock rate. As a conclusion, we give performance goals and simulation results.

Paper Details

Date Published: 1 January 1990
PDF: 11 pages
Proc. SPIE 1293, Applications of Artificial Intelligence VIII, (1 January 1990); doi: 10.1117/12.21138
Show Author Affiliations
Jean-Claude Heudin, SODIMA SA (France)
Christophe Metivier, SODIMA SA (France)

Published in SPIE Proceedings Vol. 1293:
Applications of Artificial Intelligence VIII
Mohan M. Trivedi, Editor(s)

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