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Proceedings Paper

GaAs 800-mb/s serial communications chip set
Author(s): Kelvin G. Hickman
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Paper Abstract

A high-speed communications chip set based on a 1500-gate structured cell gate array, designed specifically for interprocessor communications in multiprocessor environments has been developed. Needing a minimum of support logic, these three chips provide all link functions, including parallel/serial and serial/parallel conversion, data encoding/decoding, idle/quiet line detection, data clock phase recovery, and link error indicators. The link clock rate is 1 GHz, supporting a data rate of 800 megabit/second.

Paper Details

Date Published: 1 October 1990
PDF: 7 pages
Proc. SPIE 1291, Optical and Digital Gallium Arsenide Technologies for Signal Processing Applications, (1 October 1990); doi: 10.1117/12.21015
Show Author Affiliations
Kelvin G. Hickman, E-Systems, Inc. (United States)

Published in SPIE Proceedings Vol. 1291:
Optical and Digital Gallium Arsenide Technologies for Signal Processing Applications
Mark P. Bendett; Daniel H. Butler Jr.; Arati Prabhakar; Andrew C. Yang, Editor(s)

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