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Proceedings Paper

Scaling of parasitics in mm-wave MODFETs
Author(s): Brian Hughes; Paul J. Tasker
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Paper Abstract

Parasitics must be reduced for mm-wave MODFETs to realize their high potential. The parasitic resistances must be reduced so that (1) parasitic charging time is negligible, (2) to maintain the fj/fmax ratio, and (3) noise figure and power performance are not degraded significantly. The parasitic resistance must be scaled as l/fj. The problem of backside via inductance dominating the effective input resistance of wide MODFETs is shown. The design compromises are discussed, and rules-of-thumb are presented for scaling parasitics, (e.g., T-gate size).

Paper Details

Date Published: 1 August 1990
PDF: 11 pages
Proc. SPIE 1288, High-Speed Electronics and Device Scaling, (1 August 1990); doi: 10.1117/12.20922
Show Author Affiliations
Brian Hughes, Hewlett-Packard Co. (United States)
Paul J. Tasker, Fraunhofer-IAF (Germany)

Published in SPIE Proceedings Vol. 1288:
High-Speed Electronics and Device Scaling
Lester Fuess Eastman, Editor(s)

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