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Proceedings Paper

Experimental x-ray process latitude evaluation using E-D tree analysis
Author(s): Lars W. Liebmann; Richard A. Ferguson; Ronald M. Martino; Angela C. Lamberti; J. F. Hart; R. French
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Paper Abstract

An E-D tree based analysis of experimental X-ray lithography data is presented for features characteristic of CMOS logic gate levels. Pattern-specific print biases for isolated lines (150- 250 nm) and two types of nested lines (250 nm) are characterized. Depths of gap for increasing exposure latitudes at +/- 20 nm line width control are calculated for individual features. common process window analysis is performed on the nested and isolated 250-nm patterns. The impact of reducing the nominal mask to wafer gap (35-26 micrometers ) on maximum exposure latitude is evaluated and the effect of gap reduction and overexposure on the nested to isolated print bias is examined.

Paper Details

Date Published: 19 May 1995
PDF: 10 pages
Proc. SPIE 2437, Electron-Beam, X-Ray, EUV, and Ion-Beam Submicrometer Lithographies for Manufacturing V, (19 May 1995); doi: 10.1117/12.209150
Show Author Affiliations
Lars W. Liebmann, IBM Microelectronics (United States)
Richard A. Ferguson, IBM Microelectronics (United States)
Ronald M. Martino, IBM Microelectronics (United States)
Angela C. Lamberti, IBM Microelectronics (United States)
J. F. Hart, IBM Microelectronics (United States)
R. French, IBM Microelectronics (United States)

Published in SPIE Proceedings Vol. 2437:
Electron-Beam, X-Ray, EUV, and Ion-Beam Submicrometer Lithographies for Manufacturing V
John M. Warlaumont, Editor(s)

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