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Proceedings Paper

A facile route for fabricating graphene nanoribbon array transistors using graphoepitaxy of a symmetric block copolymer
Author(s): Jonathan W. Choi; Myungwoong Kim; Nathaniel S. Safron; Eungnak Han; Michael S. Arnold; Padma Gopalan
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Paper Abstract

We report a facile route to form densely packed graphene nanoribbon (GNR) arrays via graphoepitaxial assembly of symmetric P(S-b-MMA). Since guiding channels for graphoepitaxy are the source and drain electrodes in field effect transistor (FET) geometry, we avoid laborious nanopatterning and FET device fabrication processes. By grafting a random copolymer brush on the graphene FET device, perpendicular lamellar domains are aligned normal to the electrode direction, resulting in line arrays connecting the two electrodes. Through optimization of the reactive ion etching conditions, the vertically oriented lamellar domains were transferred to the underlying graphene, leading to GNR arrays that act as conducting channels. This is a simple and efficient fabrication process using the fundamental concepts developed for the graphoepitaxial assembly of symmetric BCPs to create densely packed sub- 20 nm GNR arrays, compared to conventional fabrication process.

Paper Details

Date Published: 17 March 2015
PDF: 10 pages
Proc. SPIE 9428, Advanced Etch Technology for Nanopatterning IV, 94280T (17 March 2015); doi: 10.1117/12.2085836
Show Author Affiliations
Jonathan W. Choi, Univ. of Wisconsin-Madison (United States)
Myungwoong Kim, Univ. of Wisconsin-Madison (United States)
Nathaniel S. Safron, Univ. of Wisconsin-Madison (United States)
Eungnak Han, Univ. of Wisconsin-Madison (United States)
Michael S. Arnold, Univ. of Wisconsin-Madison (United States)
Padma Gopalan, Univ. of Wisconsin-Madison (United States)

Published in SPIE Proceedings Vol. 9428:
Advanced Etch Technology for Nanopatterning IV
Qinghuang Lin; Sebastian U. Engelmann; Ying Zhang, Editor(s)

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