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Proceedings Paper

Dry etch challenges for CD shrinkage in memory process
Author(s): Takaya Matsushita; Takanori Matsumoto; Hidefumi Mukai; Suigen Kyoh; Kohji Hashimoto
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Paper Abstract

Line pattern collapse attracts attention as a new problem of the L&S formation in sub-20nm H.P feature. Line pattern collapse that occurs in a slight non-uniformity of adjacent CD (Critical dimension) space using double patterning process has been studied with focus on micro-loading effect in Si etching. Bias RF pulsing plasma etching process using low duty cycle helped increase of selectivity Si to SiO2. In addition to the effect of Bias RF pulsing process, the thin mask obtained from improvement of selectivity has greatly suppressed micro-loading in Si etching. However it was found that micro-loading effect worsen again in sub-20nm space width. It has been confirmed that by using cycle etch process to remove deposition with CFx based etching micro-loading effect could be suppressed. Finally, Si etching process condition using combination of results above could provide finer line and space without "line pattern collapse" in sub-20nm.

Paper Details

Date Published: 17 March 2015
PDF: 7 pages
Proc. SPIE 9428, Advanced Etch Technology for Nanopatterning IV, 942807 (17 March 2015); doi: 10.1117/12.2085628
Show Author Affiliations
Takaya Matsushita, Toshiba Corp. Semiconductor and Storage Company (Japan)
Takanori Matsumoto, Toshiba Corp. Semiconductor and Storage Company (Japan)
Hidefumi Mukai, Toshiba Corp. Semiconductor and Storage Company (Japan)
Suigen Kyoh, Toshiba Corp. Semiconductor and Storage Company (Japan)
Kohji Hashimoto, Toshiba Corp. Semiconductor and Storage Company (Japan)


Published in SPIE Proceedings Vol. 9428:
Advanced Etch Technology for Nanopatterning IV
Qinghuang Lin; Sebastian U. Engelmann; Ying Zhang, Editor(s)

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