At present, single-slope analog-to-digital convertor (ADC) is widely used in the readout circuits of CMOS image sensor (CIS) while its main drawback is the high demand for the system clock frequency. The more pixels and higher ADC resolution the image sensor system needs, the higher system clock frequency is required. To overcome this problem in high dynamic range CIS system, this paper presents a 12-bit 500-KS/s cyclic ADC, in which the system clock frequency is 5MHz. Therefore, comparing with the system frequency of 2^N×f_S for the single-slope ADC, where f_S, N is the sampling frequency and resolution, respectively, the higher ADC resolution doesn’t need the higher system clock frequency. With 0.18μm CMOS process, the circuit layout is realized and occupies an area of 8μm×374μm. Post simulation results show that Signal-to-Noise-and-Distortion-Ratio (SNDR) and Efficient Number of Bit (ENOB) reaches 63.7dB and 10.3bit, respectively.

Date Published: 13 March 2015
PDF: 7 pages
Proc. SPIE 9403, Image Sensors and Imaging Systems 2015, 94030K (13 March 2015); doi: 10.1117/12.2083269

Published in SPIE Proceedings Vol. 9403:
Image Sensors and Imaging Systems 2015
Ralf Widenhorn; Antoine Dupret, Editor(s)