We present a vision for transceiver integration on a 3 μm SOI waveguide platform for systems scalable to Pb/s. We also present experimental results from the first building blocks developed in the EU-funded RAPIDO project. At 1.3 μm wavelength 80 Gb/s per wavelength is to be achieved using hybrid integration of III-V optoelectronics on SOI. Goals include athermal operation, low-loss I/O coupling, advanced modulation formats and packet switching. An example of the design results is an interposer chip that consists of 12 μm thick SOI waveguides locally tapered down to 3 μm to provide low-loss coupling between an optical single-mode fiber array and the 3 μm SOI chip. First example of experimental results is a 4x4 cyclic AWGs with 5 nm channel spacing, 0.4 dB/facet fiber coupling loss, 3.5 dB center-tocenter loss, and -23 dB adjacent channel crosstalk in 3.5x1.5 mm² footprint. The second example result is a new VCSEL design that was demonstrated to have up to 40 Gb/s operation at 1.55 μm.

Date Published: 3 April 2015
PDF: 10 pages
Proc. SPIE 9368, Optical Interconnects XV, 93680B (3 April 2015); doi: 10.1117/12.2079682

Published in SPIE Proceedings Vol. 9368:
Optical Interconnects XV
Henning Schröder; Ray T. Chen, Editor(s)