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Proceedings Paper

Very large scale integration (VLSI) implementation of block-based predictive Rice codec
Author(s): Chien-Min Huang; Alan W. Shaw; Richard W. Harris
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Paper Abstract

This paper presents a VLSI implementation of the lossless block-based predictive Rice codec (BPRC). The BPRC uses an adaptive predictive coding algorithm to remove the redundancy in the image, codes the residue using an entropy coder. This algorithm can adapt well to local images statistics. The codec chip will encode 4 to 16-bit pixels at 10 Mpixels/sec input, and decode at 10 Mpixels/sec output. For images of normal size it requires little supports circuitry, only input data formatting and output data defomatting. Large images can be supported with external FIFOs.

Paper Details

Date Published: 21 April 1995
PDF: 11 pages
Proc. SPIE 2501, Visual Communications and Image Processing '95, (21 April 1995); doi: 10.1117/12.206744
Show Author Affiliations
Chien-Min Huang, Utah State Univ. (United States)
Alan W. Shaw, Utah State Univ. (United States)
Richard W. Harris, Utah State Univ. (United States)

Published in SPIE Proceedings Vol. 2501:
Visual Communications and Image Processing '95
Lance T. Wu, Editor(s)

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