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Proceedings Paper

A reconfigurable ASIP for high-throughput and flexible FFT processing in SDR environment
Author(s): Ting Chen; Hengzhu Liu; Botao Zhang
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Paper Abstract

This paper presents a high-throughput and reconfigurable processor for fast Fourier transformation (FFT) processing based on SDR methodology. It adopts application specific instruction-set (ASIP) and single instruction multiple data (SIMD) architecture to exploit the parallelism of butterfly operations in FFT algorithm. Moreover, a novel 3-dimension multi-bank memory is proposed for parallel conflict-free accesses. The overall throughput and power-efficiency are greatly enhanced by parallel and streamline processing. A test chip supporting 64~2048-point FFT is setup for experiment. Logic synthesis reveals a maximum clock frequency of 500MHz and an area of 0.49 mm2 for the processor's logic using a low power 45-nm technology, and the dynamic power estimation is about 96.6mW. Compared with previous works, our FFT ASIP achieves a higher energy-efficiency with relative low area cost.

Paper Details

Date Published: 16 April 2014
PDF: 6 pages
Proc. SPIE 9159, Sixth International Conference on Digital Image Processing (ICDIP 2014), 91590M (16 April 2014); doi: 10.1117/12.2064164
Show Author Affiliations
Ting Chen, National Univ. of Defense Technology (China)
Hengzhu Liu, National Univ. of Defense Technology (China)
Botao Zhang, National Univ. of Defense Technology (China)

Published in SPIE Proceedings Vol. 9159:
Sixth International Conference on Digital Image Processing (ICDIP 2014)
Charles M. Falco; Chin-Chen Chang; Xudong Jiang, Editor(s)

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