In this paper, the implementations of clock and carrier recovery in digital domain are analyzed. Hardware implementation details, resources estimation and real-time results are presented. Analog-to-Digital Converters (ADC), operating at 1.25Gsa/s, and a Virtex-6 Field-Programmable Gate Array (FPGA), have been used, allowing the implementation of a real-time Quadrature Phase Shift Keying (QPSK) system operating at 1.25Gb/s. The real-time mode operation is successfully demonstrated over 80 km of Standard Single Mode Fiber (SSMF).

Date Published: 22 August 2014
PDF: 7 pages
Proc. SPIE 9286, Second International Conference on Applications of Optics and Photonics, 92864M (22 August 2014); doi: 10.1117/12.2063761

Published in SPIE Proceedings Vol. 9286:
Second International Conference on Applications of Optics and Photonics
Manuel Filipe P. C. Martins Costa; Rogério Nunes Nogueira, Editor(s)