The rapid evolution of commercial FPGAs and analog ICs has enabled the development of Archon, a new modular high performance astronomical CCD controller. CCD outputs are digitized by 16-bit 100 MHz ADCs with differential AC-coupled preamplifiers. The raw data stream from an ADC can be stored in parallel with standard image data into three onboard 512 MB frame buffers. Pixel values are computed using digital correlated double sampling. At low pixel rates (< 1 MHz), the dynamic range achievable by averaging hundreds of ADC samples per pixel can exceed 16 bits, so an option to store 32 bits per pixel is provided. CCD clocks are generated by 14-bit 100 MHz DACs. The scripted timing core driving the clocks can generate a new target voltage for each clock every 10 ns, and the clock slew rates are individually programmable. CCD biases are derived from 16-bit DACs, are continuously monitored for voltage and current, and power up and down in a customizable sequence. Communication between the controller and a host computer occurs over a gigabit Ethernet interface (fiber or copper). A CCD configuration is specified by a simple text file. Together, these features simplify the tuning and debugging of scientific CCDs, and enable CCD-limited imaging. I present details of the controller architecture, examples of CCD tuning, and measured performance data of the controller alone (dynamic range of 108 dB at 100 kHz and 98 dB at 1 MHz) and in combination with an STA1600LN CCD.

Date Published: 28 July 2014
PDF: 11 pages
Proc. SPIE 9147, Ground-based and Airborne Instrumentation for Astronomy V, 91475B (28 July 2014); doi: 10.1117/12.2058402

Published in SPIE Proceedings Vol. 9147:
Ground-based and Airborne Instrumentation for Astronomy V
Suzanne K. Ramsay; Ian S. McLean; Hideki Takami, Editor(s)