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Proceedings Paper

Wafer-level 3D integration with 5 micron interconnect pitch for infrared imaging applications
Author(s): Matthew Lueck; John Lannon Jr.; Chris Gregory; Dean Malta; A. Huffman; Dorota S. Temple
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Paper Abstract

The use of 3D integration technology in focal plane array imaging devices has been shown to increase imaging capability while simultaneously decreasing device area and power consumption, as compared to analogous 2D designs. A key enabling technology for 3D integration is the use of high density metal-metal bonding to form pixel-level interconnects between device layers. In this paper, we review recent progress in high density, sub-10 μm pitch interconnect bonding for 3D integration of imaging systems. Specifically, we will present results from successful demonstrations of the use of Cu microbumps for the interconnection of 5 μm pitch 640×512 and 1280×1024 arrays. Operability of the arrays of bonded interconnects in two-layer silicon die stacks was greater than 99.99% with good electrical isolation between bonds.

Paper Details

Date Published: 21 May 2014
PDF: 8 pages
Proc. SPIE 9100, Image Sensing Technologies: Materials, Devices, Systems, and Applications, 910009 (21 May 2014); doi: 10.1117/12.2058166
Show Author Affiliations
Matthew Lueck, RTI International (United States)
John Lannon Jr., RTI International (United States)
Chris Gregory, RTI International (United States)
Dean Malta, RTI International (United States)
A. Huffman, RTI International (United States)
Dorota S. Temple, RTI International (United States)

Published in SPIE Proceedings Vol. 9100:
Image Sensing Technologies: Materials, Devices, Systems, and Applications
Nibir K. Dhar; Achyut K. Dutta, Editor(s)

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