The Thompson cloud microphysics scheme is a sophisticated cloud microphysics scheme in the Weather Research and Forecasting (WRF) model. The scheme is very suitable for massively parallel computation as there are no interactions among horizontal grid points. Compared to the earlier microphysics schemes, the Thompson scheme incorporates a large number of improvements. Thus, we have optimized the speed of this important part of WRF. Intel Many Integrated Core (MIC) ushers in a new era of supercomputing speed, performance, and compatibility. It allows the developers to run code at trillions of calculations per second using the familiar programming model. In this paper, we present our results of optimizing the Thompson microphysics scheme on Intel Many Integrated Core Architecture (MIC) hardware. The Intel Xeon Phi coprocessor is the first product based on Intel MIC architecture, and it consists of up to 61 cores connected by a high performance on-die bidirectional interconnect. The coprocessor supports all important Intel development tools. Thus, the development environment is familiar one to a vast number of CPU developers. Although, getting a maximum performance out of MICs will require using some novel optimization techniques. Those optimization techniques are discusses in this paper. The results show that the optimization improved MIC performance by 3.4x. Furthermore, the optimized MIC code is 7.0x faster than the optimized multi-threaded code on the four CPU cores of a single socket Intel Xeon E5-2603 running at 1.8 GHz.

Date Published: 28 May 2014
PDF: 12 pages
Proc. SPIE 9124, Satellite Data Compression, Communications, and Processing X, 91240Q (28 May 2014); doi: 10.1117/12.2055038

Published in SPIE Proceedings Vol. 9124:
Satellite Data Compression, Communications, and Processing X
Bormin Huang; Chein-I Chang; José Fco. López, Editor(s)