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Proceedings Paper

Enabling more capability within smaller pixels: advanced wafer-level process technologies for integration of focal plane arrays with readout electronics
Author(s): Dorota S. Temple; Erik P. Vick; Matthew R Lueck; Dean Malta; Mark R. Skokan; Christopher M. Masterjohn; Mark S. Muzilla
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Paper Abstract

Over the past decade, the development of infrared focal plane arrays (FPAs) has seen two trends: decreasing of the pixel size and increasing of signal-processing capability at the device level. Enabling more capability within smaller pixels can be achieved through the use of advanced wafer-level processes for the integration of FPAs with silicon (Si) readout integrated circuits (ROICs). In this paper, we review the development of these wafer-level integration technologies, highlighting approaches in which the infrared sensor is integrated with three-dimensional ROIC stacks composed of multiple layers of Si circuitry interconnected using metal-filled through-silicon vias.

Paper Details

Date Published: 21 May 2014
PDF: 7 pages
Proc. SPIE 9100, Image Sensing Technologies: Materials, Devices, Systems, and Applications, 91000L (21 May 2014); doi: 10.1117/12.2054106
Show Author Affiliations
Dorota S. Temple, RTI International (United States)
Erik P. Vick, RTI International (United States)
Matthew R Lueck, RTI International (United States)
Dean Malta, RTI International (United States)
Mark R. Skokan, DRS Technologies, Inc. (United States)
Christopher M. Masterjohn, DRS Technologies, Inc. (United States)
Mark S. Muzilla, DRS Technologies, Inc. (United States)


Published in SPIE Proceedings Vol. 9100:
Image Sensing Technologies: Materials, Devices, Systems, and Applications
Nibir K. Dhar; Achyut K. Dutta, Editor(s)

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