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Proceedings Paper

Design technology co-optimization for a robust 10nm Metal1 solution for logic design and SRAM
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Paper Abstract

The density requirement expected for the 10nm node continues to increase the pressure on patterning. With the frontend of line adopting a regular layout (mostly unidirectional), most of the complexity needed for a functional chip ends up in the interconnect layer and Metal1. Assuming that Extreme Ultra Violet Lithography (EUVL) will not be ready for the early stage of 10nm production but only for high volume manufacturing, we have studied how ArF immersion lithography can be extended for Metal1 to sustain the development of the technology as well as the early production phase, while at the same time remaining compatible with an EUVL single patterning solution. We show how close interaction between design, process and computational lithography leads to a Metal1 triple patterning solution using Negative Tone Development (NTD), and how the same design solution can be supported by EUVL single patterning. Particular attention will be paid to line end printability performance, both tip to tip and tip to line, as we believe it is a key parameter to define the best compromise between lithography performance and design density.

Paper Details

Date Published: 28 March 2014
PDF: 13 pages
Proc. SPIE 9053, Design-Process-Technology Co-optimization for Manufacturability VIII, 90530Q (28 March 2014); doi: 10.1117/12.2048079
Show Author Affiliations
Boris Vandewalle, IMEC (Belgium)
Bharani Chava, IMEC (Belgium)
Sushil Sakhare, IMEC (Belgium)
Julien Ryckaert, IMEC (Belgium)
Mircea Dusa, ASML Belgium BVBA (Belgium)

Published in SPIE Proceedings Vol. 9053:
Design-Process-Technology Co-optimization for Manufacturability VIII
John L. Sturtevant; Luigi Capodieci, Editor(s)

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