In high-speed banknote sorting system, to real-time deal with massive data and complex algorithm is required. This paper proposes an embedded processing system, which realizing the high-speed image acquisition and real-time processing of banknote image. The system is a customized and flexible architecture consisting of one large scale FPGA and four high performance DSP chips. The five processors have good communication with each other by RapidIO BUS. After evaluating the system-calculating overhead, the data throughput, and the hardware characteristics, we presents the whole processing program systematically running in FPGA and DSPs. In order to make full use of the advantage of FPGA highly parallelism and DSP deeply pipeline, the FPGA is designed for running parallel algorithms with large amount of calculation but low complexity of control flow, and the rest of algorithms are assigned to the four DSPs relatively. Finally, the whole program of image processing at the speed of 40 frames per second is realized on the embedded processing platform. The system has been successfully used in high-speed banknote sorting device, which has showed stable and reliable properties. And it also has excellent performance in processing ability with the verification of large scale operation.

Date Published: 19 December 2013
PDF: 13 pages
Proc. SPIE 9045, 2013 International Conference on Optical Instruments and Technology: Optoelectronic Imaging and Processing Technology, 90450M (19 December 2013); doi: 10.1117/12.2034253

Published in SPIE Proceedings Vol. 9045:
2013 International Conference on Optical Instruments and Technology: Optoelectronic Imaging and Processing Technology
Xinggang Lin; Jesse Zheng, Editor(s)