This paper presents the tethered Forth system dedicated for testing and debugging of FPGA based electronic systems. Use of the Forth language allows to interactively develop and run complex testing or debugging routines. The solution is based on a small, 16-bit soft core CPU, used to implement the Forth Virtual Machine. Thanks to the use of the tethered Forth model it is possible to minimize usage of the internal RAM memory in the FPGA. The function of the intelligent terminal, which is an essential part of the tethered Forth system, may be fulfilled by the standard PC computer or by the smartphone. System is implemented in Python (the software for intelligent terminal), and in VHDL (the IP core for FPGA), so it can be easily ported to different hardware platforms. The connection between the terminal and FPGA may be established and disconnected many times without disturbing the state of the FPGA based system. The presented system has been verified in the hardware, and may be used as a tool for debugging, testing and even implementing of control algorithms for FPGA based systems.

Date Published: 25 October 2013
PDF: 8 pages
Proc. SPIE 8903, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2013, 89031M (25 October 2013); doi: 10.1117/12.2033279

Published in SPIE Proceedings Vol. 8903:
Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2013
Ryszard S. Romaniuk, Editor(s)