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Proceedings Paper

Architectural evaluation of dynamic and partial reconfigurable systems designed with DREAMS tool
Author(s): Andrés Otero; Ángel Gallego; Eduardo de la Torre; Teresa Riesgo
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Paper Abstract

Benefits of dynamic and partial reconfigurable systems are increasingly being more accepted by the industry. For this reason, SRAM-based FPGA manufacturers have improved, or even included for the first time, the support they offer for the design of this kind of systems. However, commercial tools still offer a poor flexibility, which leads to a limited efficiency. This is witnessed by the overhead introduced by the communication primitives, as well as by the inability to relocate reconfigurable modules, among others. For this reason, authors have proposed an academic design tool called DREAMS, which targets the design of dynamically reconfigurable systems. In this paper, main features offered by DREAMS are described, comparing them with existing commercial and academic tools. Moreover, a graphic user interface (GUI) is originally described in this work, with the aim of simplifying the design process, as well as to hide the low level device dependent details to the system designer. The overall goal is to increase the designer productivity. Using the graphic interface, different reconfigurable architectures are provided as design examples. Among them, both conventional slot-based architectures and mesh type designs have been included.

Paper Details

Date Published: 28 May 2013
PDF: 17 pages
Proc. SPIE 8764, VLSI Circuits and Systems VI, 87640H (28 May 2013); doi: 10.1117/12.2021271
Show Author Affiliations
Andrés Otero, Univ. Politécnica de Madrid (Spain)
Ángel Gallego, Univ. Politécnica de Madrid (Spain)
Eduardo de la Torre, Univ. Politécnica de Madrid (Spain)
Teresa Riesgo, Univ. Politécnica de Madrid (Spain)

Published in SPIE Proceedings Vol. 8764:
VLSI Circuits and Systems VI
Teresa Riesgo; Massimo Conti, Editor(s)

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