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Proceedings Paper

A hierarchical scheduling and management solution for dynamic reconfiguration in FPGA-based embedded systems
Author(s): T. Cervero; A. Gómez; S. López; R. Sarmiento; J. Dondo; F. Rincón; J. C. López
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Paper Abstract

One of the limiting factors that have prevented a widely dissemination of the reconfigurable technology is the absence of an appropriate model for certain target applications capable of offering a reliable control. Moreover, the lack of flexible and easy-to-use scheduling and management systems are also relevant drawbacks to be considered. Under static scenarios, it is relatively easy to schedule and manage the reconfiguration process since all the variations corresponding to predetermined and well-known tasks. However, the difficulty increases when the adaptation needs of the overall system change semi-randomly according to the environmental fluctuations. In this context, this work proposes a change in the paradigm of dynamically reconfigurable systems, by attending to the dynamically reconfigurable control problematic as a whole, in which the scheduling and the placement issues are packed together as a hierarchical management structure, interacting together as one entity from the system point of view, but performing their tasks with certain degree of independence each other. In this sense, the top hierarchical level corresponds with a dynamic scheduler in charge of planning and adjusting all the reconfigurable modules according to the variations of the external stimulus. The lower level interacts with the physical layer of the device by means of instantiating, relocating, removing a reconfigurable module following the scheduler’s instructions. In regards to how fast is the proposed solution, the total partial reconfiguration time achieved with this proposal has been measured and compared with other two approaches: 1) using traditional Xilinx’s tools; 2) using an optimized version of the Xilinx's drivers. The collected numbers demonstrate that our solution reaches a gain up to 10 times faster than the other approaches.

Paper Details

Date Published: 28 May 2013
PDF: 9 pages
Proc. SPIE 8764, VLSI Circuits and Systems VI, 87640J (28 May 2013); doi: 10.1117/12.2021270
Show Author Affiliations
T. Cervero, Univ. de Las Palmas de Gran Canaria (Spain)
A. Gómez, Univ. de Las Palmas de Gran Canaria (Spain)
S. López, Univ. de Las Palmas de Gran Canaria (Spain)
R. Sarmiento, Univ. de Las Palmas de Gran Canaria (Spain)
J. Dondo, Univ. de Castilla-La Mancha (Spain)
F. Rincón, Univ. de Castilla-La Mancha (Spain)
J. C. López, Univ. de Castilla-La Mancha (Spain)

Published in SPIE Proceedings Vol. 8764:
VLSI Circuits and Systems VI
Teresa Riesgo; Massimo Conti, Editor(s)

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