Electronics advancement demands integration of large number of transistors /capacitors in a very small chip area. Thus, small feature size fabrication is a critical issue and precise fabrications of features under nano scale require advanced lithographic and etching techniques. In this paper, MOS capacitor with TiN metal-gate and HfO₂ dielectric layer was fabricated in a world class clean-room lab in KTH. There, state-of-the art lithography stepper, advanced etching machines and all important clean-room fabrication facilities were used for successful fabrication of the nano-dimension MOS capacitor, whose detailed experimental procedures and results are exhaustively dealt in this report.

Date Published: 29 March 2013
PDF: 4 pages
Proc. SPIE 8685, Advanced Etch Technology for Nanopatterning II, 86850W (29 March 2013);

Published in SPIE Proceedings Vol. 8685:
Advanced Etch Technology for Nanopatterning II
Ying Zhang; Gottlieb S. Oehrlein; Qinghuang Lin, Editor(s)