A system-level implementation of FFT architecture for long data series is presented. It exploits opportunities provided by the newest Programmable System-on-Chips (PSoC) to perform such intensive algorithms. The proposed strategy relies on a balanced partitioning of computational e ort between an embedded ARM processor and an on-purpose designed FFT module based on a Radix-2 algorithm. The external memories are used to accommodate the large amount of complex data and twiddle coefficients. The embedded controller is purposely programmed to allow the high-level management of the algorithm and the correct flow of data among peripherals, without need of extra control logic. The proposed architecture can be easily reconfigured, in order to change input data length. When implemented using a Microsemi A2F500 SmartFusion FPGA chip, it consumes approximately 61% of available logic resources to compute a 65536-point FFT.

Date Published: 28 May 2013
PDF: 7 pages
Proc. SPIE 8764, VLSI Circuits and Systems VI, 87640E (28 May 2013); doi: 10.1117/12.2016988

Published in SPIE Proceedings Vol. 8764:
VLSI Circuits and Systems VI
Teresa Riesgo; Massimo Conti, Editor(s)