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Proceedings Paper

Reducing flicker noise up-conversion in a 65nm CMOS VCO in the 1.6 to 2.6 GHz band
Author(s): Federico Pepe; Andrea Bonfanti; Salvatore Levantino; Carlo Samori; Andrea Leonardo Lacaita
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Paper Abstract

The demand of voltage-controlled oscillators (VCOs) with a broad tuning range can lead to unacceptable degradation of the 1/f3 phase-noise component if traditional voltage-biased topologies are implemented. In this paper, a novel VCO architecture is proposed, where a segmented transconductor tailors the negative-gm depending on the operating range to ensure that flicker noise up-conversion remains minimal. The implemented oscillator covers both 4G and WiMAX 2.5-GHz operation modes and achieves a 10-dB reduction of the 1/f3 phase noise without impairing the 1/f2 phase-noise performance.

Paper Details

Date Published: 28 May 2013
PDF: 9 pages
Proc. SPIE 8764, VLSI Circuits and Systems VI, 876403 (28 May 2013); doi: 10.1117/12.2016841
Show Author Affiliations
Federico Pepe, Politecnico di Milano (Italy)
Andrea Bonfanti, Politecnico di Milano (Italy)
Salvatore Levantino, Politecnico di Milano (Italy)
Carlo Samori, Politecnico di Milano (Italy)
Andrea Leonardo Lacaita, Politecnico di Milano (Italy)

Published in SPIE Proceedings Vol. 8764:
VLSI Circuits and Systems VI
Teresa Riesgo; Massimo Conti, Editor(s)

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