Proceedings Paper
FPGA implementation of a software-defined radar processor| Format | Member Price | Non-Member Price |
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Paper Abstract
A unified digital pulse compression processor is introduced as a radar-application-specific-processor (RASP) architecture for the next generation of adaptive radar. Based on traditional pulse compression matched filter and correlation receiver, the processor integrates specific designs to handle waveform diversities, which includes random noise waveforms, as well as digital transceiver self-reconfiguration for adaptive radars. Initial prototype of this processor is implemented with the latest Xilinx FPGA device and tested with an RF spaceborne radar transceiver testbed. Initial validation results show the effectiveness of real-time processing and engineering concepts.
Paper Details
Date Published: 31 May 2013
PDF: 10 pages
Proc. SPIE 8714, Radar Sensor Technology XVII, 871403 (31 May 2013); doi: 10.1117/12.2016034
Published in SPIE Proceedings Vol. 8714:
Radar Sensor Technology XVII
Kenneth I. Ranney; Armin Doerry, Editor(s)
PDF: 10 pages
Proc. SPIE 8714, Radar Sensor Technology XVII, 871403 (31 May 2013); doi: 10.1117/12.2016034
Show Author Affiliations
Hernan Suarez, The Univ. of Oklahoma (United States)
Yan Rockee Zhang, The Univ. of Oklahoma (United States)
Published in SPIE Proceedings Vol. 8714:
Radar Sensor Technology XVII
Kenneth I. Ranney; Armin Doerry, Editor(s)
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