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Proceedings Paper

Rethinking ASIC design with next generation lithography and process integration
Author(s): Kaushik Vaidyanathan; Renzhi Liu; Lars Liebmann; Kafai Lai; Andrzej Strojwas; Larry Pileggi
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Paper Abstract

Given the deployment delays for EUV, several next generation lithography (NGL) options are being actively researched. Several cost-effective NGL solutions, such as self-aligned double patterning through sidewall image transfer (SIT) and directed self-assembly (DSA), in conjunction with process integration challenges, mandate grating-like pattern design. As part of the GRATEdd project, we have evaluated the design cost of grating-based design for ASICs (application specific ICs). Based on our observations we have engineered fundamental changes to the primary ASIC design components to make scaling affordable and useful in deeply scaled sub-20 nm technologies: unidirectional-M1 based standard cells, application-specific smart SRAM synthesis, and statistical and self-healing analog design.

Paper Details

Date Published: 29 March 2013
PDF: 15 pages
Proc. SPIE 8684, Design for Manufacturability through Design-Process Integration VII, 86840C (29 March 2013); doi: 10.1117/12.2014374
Show Author Affiliations
Kaushik Vaidyanathan, Carnegie Mellon Univ. (United States)
Renzhi Liu, Carnegie Mellon Univ. (United States)
Lars Liebmann, IBM Corp. (United States)
Kafai Lai, IBM Corp. (United States)
Andrzej Strojwas, Carnegie Mellon Univ. (United States)
Larry Pileggi, Carnegie Mellon Univ. (United States)


Published in SPIE Proceedings Vol. 8684:
Design for Manufacturability through Design-Process Integration VII
Mark E. Mason; John L. Sturtevant, Editor(s)

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