The industry’s march towards higher transistor density has called for an ever-increasing number of interconnect levels in logic devices. The historic transition from aluminum to copper was necessary in reducing timing delays while future technology nodes presents an opportunity for new materials and patterning techniques. One material for consideration is graphene, a single atomic layer of carbon atoms. Graphene is known to have excellent electrical properties [1], driving strong interest in its integration into the wafer fabrication processes for future electronics [2], and its ballistic transport properties give promise for use in on-chip interconnects [3]. This study demonstrates the feasibility of a direct electron beam lithography technique to pattern sub-5nm metallic graphene ribbons, without using a mask or photoresist, to act as next generation interconnects. Sub-5nm monolayer and multilayer graphene ribbons were patterned using a focused electron beam in a transmission electron microscope (TEM) through direct knock-on ejection of carbon atoms. These ribbons were measured during fabrication to quantify their electrical performance. Multilayered graphene nanoribbons were found to sustain current densities in excess of 10⁹ A/cm², orders of magnitude higher than copper, while monolayer graphene provides comparable performance to copper but at the level of a single atomic layer. High volume manufacturing could utilize wafer-size chemical vapor deposition (CVD) graphene [4] transferred directly onto the substrate paired with a direct write multi-beam tool to knock off carbon atoms for patterning of nanometer sized interconnects. The patterning technique introduced here allows for the fabrication of small foot-print high performance next generation graphene interconnects that bypass the use of a mask and resist process.

Date Published: 26 March 2013
PDF: 6 pages
Proc. SPIE 8680, Alternative Lithographic Technologies V, 86802F (26 March 2013); doi: 10.1117/12.2013724

Published in SPIE Proceedings Vol. 8680:
Alternative Lithographic Technologies V
William M. Tong, Editor(s)