Proceedings Paper
Implement of time division multiplexing high speed programmable viterbi decoder IP core| Format | Member Price | Non-Member Price |
|---|---|---|
| $17.00 | $21.00 |
Paper Abstract
The programmable Time Division multiplexing high Viterbi decoder IP core is studied in this paper. According to
the characteristics of multiple communication system, the method of programmable time-division multiplexing is puts
forward, the high-performance and less resource occupy IP core is designed. Based on SMIC 0.18um CMOS technology,
the ASIC of IP core is test. The test results show that the IP core areas, power and frequency could satisfy demand of
real-time communication.
Paper Details
Date Published: 14 March 2013
PDF: 4 pages
Proc. SPIE 8768, International Conference on Graphic and Image Processing (ICGIP 2012), 87685U (14 March 2013); doi: 10.1117/12.2012476
Published in SPIE Proceedings Vol. 8768:
International Conference on Graphic and Image Processing (ICGIP 2012)
Zeng Zhu, Editor(s)
PDF: 4 pages
Proc. SPIE 8768, International Conference on Graphic and Image Processing (ICGIP 2012), 87685U (14 March 2013); doi: 10.1117/12.2012476
Show Author Affiliations
Lan Wu, Henan Univ. of Technology (China)
Qiliang Chen, Beijing Microelectronics Technology Institute (China)
Published in SPIE Proceedings Vol. 8768:
International Conference on Graphic and Image Processing (ICGIP 2012)
Zeng Zhu, Editor(s)
© SPIE. Terms of Use
