Share Email Print

Proceedings Paper

FPGA implementation of digital down converter using CORDIC algorithm
Author(s): Ashok Agarwal; Boppana Lakshmi
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

In radio receivers, Digital Down Converters (DDC) are used to translate the signal from Intermediate Frequency level to baseband. It also decimates the oversampled signal to a lower sample rate, eliminating the need of a high end digital signal processors. In this paper we have implemented architecture for DDC employing CORDIC algorithm, which down converts an IF signal of 70MHz (3G) to 200 KHz baseband GSM signal, with an SFDR greater than 100dB. The implemented architecture reduces the hardware resource requirements by 15 percent when compared with other architecture available in the literature due to elimination of explicit multipliers and a quadrature phase shifter for mixing.

Paper Details

Date Published: 28 January 2013
PDF: 6 pages
Proc. SPIE 8760, International Conference on Communication and Electronics System Design, 87601K (28 January 2013); doi: 10.1117/12.2012307
Show Author Affiliations
Ashok Agarwal, National Institute of Technology, Warangal (India)
Boppana Lakshmi, National Institute of Technology, Warangal (India)

Published in SPIE Proceedings Vol. 8760:
International Conference on Communication and Electronics System Design
Vijay Janyani; M. Salim; K. K. Sharma, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?